The integrated services digital network (ISDN) is a general purpose digital network capable of supporting access to a wide range of interconnected services, such as voice, data, facsimile and video. ISDN achieves the support of a large variety of services by providing a standard digital network user interface. A standardized interface, including different configurations was disclosed in the I.400 series of recommendations by the CCITT in 1984.
FIG. 1 depicts a standard user network comprising a public network circuit 10 (e.g., a central office switch or PABX) and a network termination unit (NT) 11 which terminates a trunk line (digital subscriber bus) 13 from the public network circuit 10. A plurality of terminal equipments (TEs) 21, 22, 23, 24, 25, 26, 27, 28 are connected via a basic rate S interface bus 12 in a point to multipoint configuration which supports two way communication between the NT 11 and the individual TEs 21, 22,. . . , 28. Three data terminal equipments (DTEs) 31, 32, 33 are connected to the TEs 21, 22, 23, respectively.
According to the CCITT I.400 recommendations, the basic rate interface provides two full-duplex 64 kbit/sec channels (called B-channels) for communication and a D-channel for signaling. Data transmitted in the B-channels is transmitted over the S interface bus 12 as a bitstream organized into groups of eight bits (octets). In a standard user network with a basic rate interface, only one DTE may use a B-channel at one time. Thus, only two DTEs may obtain ISDN data service concurrently.
Illustratively, the DTEs 31, 32, 33 have standard interfaces, called V-series type interfaces. The DTEs 31, 32, 33 may be connected to the ISDN network via the TEs 21, 22, 23 according to the V.110 series of recommendations by the CCITT. As per these recommendations, the TEs 21, 22, 23 provide several functions for connecting such DTEs to the ISDN network including adapting the rate, in which data is transmitted from the DTE 31, 32 or 33, to the ISDN B-channel data rate. The V.110 recommendations include data rate adaption protocols for both synchronously transmitted data and asynchronously transmitted data. Each is now described separately in detail.
1. Synchronous data rate adaption
The data rate adaption performed within each TE 21, 22, 23 according to the V.110 recommendations is illustrated by the functional blocks shown in FIG. 2. As depicted, data transmitted at a user data rate from the DTE (e.g., the DTE 31) is received in the block RA1. In the block RA1, the rate of the data received from the DTE (e.g., the DTE 31) is converted to an intermediate data rate 2.sup.k .multidot.8 kbits/sec where k=0, 1 or 2 depending on the user data rate at which the DTE transmits the data. Table 1 lists a selection of V-series interface data rates up to 19,200 bits/sec and the corresponding intermediate data rate used in the block RA1 .
TABLE 1 ______________________________________ Data signalling rate Intermediate rate ______________________________________ 600 8 kbits/sec 1200 8 kbits/sec 2400 8 kbits/sec 4800 8 kbits/sec 7200 16 kbits/sec 9600 16 kbits/sec 12000 32 kbits/sec 14400 32 kbits/sec 19200 32 kbits/sec ______________________________________
The data is outputted from the block RA1 within a bitstream which is organized into frames. A template frame structure used in converting a user data rate to an intermediate data rate in the block RA1 is illustrated as a two-dimensional array in table 2.
TABLE 2 ______________________________________ Octet Bit Number No. 1 2 3 4 5 6 7 8 ______________________________________ 0 0 0 0 0 0 0 0 0 1 1 D1 D2 D3 D4 D5 D6 S1 2 1 D7 D8 D9 D10 D11 D12 X 3 1 D13 D14 D15 D16 D17 D18 S3 4 1 D19 D20 D21 D22 D23 D24 S4 5 1 E1 E2 E3 E4 E5 E6 E7 6 1 D25 D26 D27 D28 D29 D30 S6 7 1 D31 D32 D33 D34 D35 D36 X 8 1 D37 D38 D39 D40 D41 D42 S8 9 1 D43 D44 D45 D46 D47 D48 S9 ______________________________________
As shown, an 80 bit template frame (having 10 octets of bits) is used. The block RA1 transmits the bits of the frame in the order from left to right and from the top to the bottom. In the template frame, the octet 0 of the frame contains all `binary 0` bits. The octet 5 contains a `binary 1` followed by seven E bits E.sub.1 -E.sub.7. The octets 1-4 and 6-9 contain a `binary 1` in the first bit position of the octet, a status bit (S or X bit) in the eighth bit position and six data bits (D bits) in the second through the seventh bit positions. Tables 3a, 3b, 3c, 3d, 3e and 3f illustrate how the data bits outputted from a DTE (e.g, the DTE 31) are assigned to bit positions of the template frame in adapting each of the V-series user data rates of table 1 to a corresponding intermediate data rate.
TABLE 3a ______________________________________ 1 2 3 4 5 6 7 8 ______________________________________ 0 0 0 0 0 0 0 0 0 1 1 D1 D1 D1 D1 D1 D1 S1 2 1 D1 D1 D2 D2 D2 D2 X 3 1 D2 D2 D2 D2 D3 D3 S3 4 1 D3 D3 D3 D3 D3 D3 S4 5 1 1 0 0 E4 E5 E6 E7 6 1 D4 D4 D4 D4 D4 D4 S6 7 1 D4 D4 D5 D5 D5 D5 X 8 1 D5 D5 D5 D5 D6 D6 S8 9 1 D6 D6 D6 D6 D6 D6 S9 ______________________________________
TABLE 3b ______________________________________ 1 2 3 4 5 6 7 8 ______________________________________ 0 0 0 0 0 0 0 0 0 1 1 D1 D1 D1 D1 D2 D2 S1 2 1 D2 D2 D3 D3 D3 D3 X 3 1 D4 D4 D4 D4 D5 D5 S3 4 1 D5 D5 D6 D6 D6 D6 S4 5 1 0 1 0 E4 E5 E6 E7 6 1 D7 D7 D7 D7 D8 D8 S6 7 1 D8 D8 D9 D9 D9 D9 X 8 1 D10 D10 D10 D10 D11 D11 S8 9 1 D11 D11 D12 D12 D12 D12 S9 ______________________________________
TABLE 3c ______________________________________ 1 2 3 4 5 6 7 8 ______________________________________ 0 0 0 0 0 0 0 0 0 1 1 D1 D1 D2 D2 D3 D3 S1 2 1 D4 D4 D5 D5 D6 D6 X 3 1 D7 D7 D8 D8 D9 D9 S3 4 1 D10 D10 D11 D11 D12 D12 S4 5 1 1 1 0 E4 E5 E6 E7 6 1 D13 D13 D14 D14 D15 D15 S6 7 1 D16 D16 D17 D17 D18 D18 X 8 1 D19 D19 D20 D20 D21 D21 S8 9 1 D22 D22 D23 D23 D24 D24 S9 ______________________________________
TABLE 3d ______________________________________ 1 2 3 4 5 6 7 8 ______________________________________ 0 0 0 0 0 0 0 0 0 1 1 D1 D2 D3 D4 D5 D6 S1 2 1 D7 D8 D9 D10 F F X 3 1 D11 D12 F F D13 D14 S3 4 1 F F D15 D16 D17 D18 S4 5 1 1 0 1 E4 E5 E6 E7 6 1 D19 D20 D21 D22 D23 D24 S6 7 1 D25 D26 D27 D28 F F X 8 1 D29 D30 F F D31 D32 S8 9 1 F F D33 D34 D35 D36 S9 ______________________________________
TABLE 3e ______________________________________ 1 2 3 4 5 6 7 8 ______________________________________ 0 0 0 0 0 0 0 0 0 1 1 D1 D2 D3 D4 D5 D6 S1 2 1 D7 D8 D9 D10 D11 D12 X 3 1 D13 D14 D15 D16 D17 D18 S3 4 1 D19 D20 D21 D22 D23 D24 S4 5 1 0 1 1 E4 E5 E6 E7 6 1 D25 D26 D27 D28 D29 D30 S6 7 1 D31 D32 D33 D34 D35 D36 X 8 1 D37 D38 D39 D40 D41 D42 S8 9 1 D43 D44 D45 D46 D47 D48 S9 ______________________________________
TABLE 3f ______________________________________ 1 2 3 4 5 6 7 8 ______________________________________ 0 0 0 0 0 0 0 0 0 1 1 D1 D2 D3 D4 D5 D6 S1 2 1 D7 D8 D9 D10 F F X 3 1 D11 D12 F F D13 D14 S3 4 1 F F D15 F F F S4 5 1 0 0 1 E4 E5 E6 E7 6 1 D16 D17 D18 D19 D20 D21 S6 7 1 D22 D23 D24 D25 F F X 8 1 D26 D27 F F D28 D29 S8 9 1 F F D30 F F F S9 ______________________________________
The 48 and 56 kbit/sec V-series user data rates are adapted to the 64 kbit/sec B-channel rate in a single step by assigning bits as shown in tables 3g and 3h (or 3i), respectively.
TABLE 3g ______________________________________ Octet Bit Number No. 1 2 3 4 5 6 7 8 ______________________________________ 1 1 D1 D2 D3 D4 D5 D6 S1 2 0 D7 D8 D9 D10 D11 D12 X 3 1 D13 D14 D15 D16 D17 D18 S3 4 1 D19 D20 D21 D22 D23 D24 S4 ______________________________________
TABLE 3h ______________________________________ Octet Bit Number No. 1 2 3 4 5 6 7 8 ______________________________________ 1 D1 D2 D3 D4 D5 D6 D7 1 2 D8 D9 D10 D11 D12 D13 D14 1 3 D15 D16 D17 D18 D19 D20 D21 1 4 D22 D23 D24 D25 D26 D27 D28 1 5 D29 D30 D31 D32 D33 D34 D35 1 6 D36 D37 D38 D39 D40 D41 D42 1 7 D43 D44 D45 D46 D47 D48 D49 1 8 D50 D51 D52 D53 D54 D55 D56 1 ______________________________________
TABLE 3i ______________________________________ Octet Bit Number No. 1 2 3 4 5 6 7 8 ______________________________________ 1 D1 D2 D3 D4 D5 D6 D7 0 2 D8 D9 D10 D11 D12 D13 D14 X 3 D15 D16 D17 D18 D19 D20 D21 S3 4 D22 D23 D24 D25 D26 D27 D28 S4 5 D29 D30 D31 D32 D33 D34 D35 1 6 D36 D37 D38 D39 D40 D41 D42 1 7 D43 D44 D45 D46 D47 D48 D49 1 8 D50 D51 D52 D53 D54 D55 D56 1 ______________________________________
As shown, the bit assignments in tables 3g, 3h and 3i use a different template frame from the template frame shown in table 2.
The 600, 1200 and 2400 bit/sec user data rates are adapted to the 8 kbit/sec intermediate data rate by assigning bits as shown in tables 3a, 3b and 3c, respectively. For example, suppose the DTE 31 transmits data, e.g., 12 data bits d1,d2, . . . d12, at a 1200 bit/sec user data rate to the TE 21. The block RA1 assigns the received data bits d1-d12 to the bit positions D1-D12 of table 3b, respectively. In other words, the received bit d1 is inserted into bit positions 2-5 of octet 1, the received bit d2 is inserted into bit positions 6-7 of octet 1 and bit positions 2-3 of octet 2, etc. In addition, the bits `0,` `1` and `0` are inserted into the bit positions 2, 3, and 4, respectively of octet 5, which bit positions correspond to the E bits, E1, E2 and E3. The bits of the frame are then transmitted in the order from left to right and from top to bottom to the block RA2 at the intermediate data rate of 8 kbit/sec.
The 7200 and 14400 bit/sec user data rates are adapted to the 16 and 32 kbit/sec intermediate data rates, respectively, by assigning bits as shown in table 3d. As depicted in table 3d, a filling bit (F bit) is inserted into unused data bit locations of the template frame. The 4800, 9600 and 19,200 bit/sec user data rates are adapted to the 8, 16 and 32 kbit/sec intermediate data rates, respectively, by assigning bits as shown in table 3e. The 12000 bit/sec user data rate is adapted to the 32 kbit/sec intermediate data rate by assigning bits as shown in the table 3f. Again, a filling bit (F bit) is inserted into unused data bit locations of the template frame.
The converted data is then transferred at the intermediate data rate (2.sup.k .multidot.8 kbits/sec) from the block RA1 to the block RA2. In the block RA2, the intermediate data rate (2.sup.k .multidot.8 kbits/sec) is converted to the B-channel data rate (64 kbits/sec). (If the user data rate is 48 or 56 kbits/sec, the data rate is converted directly to the B-channel data rate in one step.) The block RA2 adapts the data rate of the bitstream outputted from the block RA1 to the B-channel data rate using a bit stuffing technique. To that end, the block RA2 outputs a bitstream which is organized into octets having a particular number of data bit positions containing bits of the received frames. The number of data bit positions depends on the intermediate data rate of the bitstream outputted from the block RA1. FIG. 3 depicts three different template octets used for adapting the 8, 16 and 32 kbit/sec intermediate data rates, respectively, to the B-channel data rate (64 kbits/sec). The order of transmission of the bits of the octets from the block RA2 is from left to right.
As depicted, each template has one or more data bit positions (b bits) into which the bits of the frames outputted from the block RA1 are inserted as they are received. For example, as bits of the frames are received at the 8 kbit/sec intermediate rate, they are inserted, in the order in which they are received, in the first bit position b.sub.1 of sequentially transmitted octets. As bits of the frames are received at the 16 kbit/sec intermediate rate, they are inserted, in the order in which they are received, into the first two bit positions b.sub.1, b.sub.2 of successive octets transmitted from the block RA2. Similarly, as bits of the frames are received at the 32 kbit/sec intermediate data rate, they are inserted, in the order in which they are received, into the first four bit positions b.sub.1, b.sub.2, b.sub.3, b.sub.4 of successive octets transmitted from the block RA2. All of the remaining bit positions of each template octet are filled with a default binary value such as `binary 1`.
Data adapted to the B-channel data rate in this manner is then transmitted from the TE (e.g., the TE 21) to the S interface bus 12. The data propagates via the NT 11 to a receiving TE which TE has conventional circuitry for reversing the above described data rate adaptions. Illustratively, the same blocks RA1 and RA2 are capable of performing the reverse data rate adaption for received data. That is, the block RA2 receives a bitstream from the B-channel at the B-channel data rate and outputs a second bitstream at an appropriate intermediate data rate (depending on the user data rate) comprising only information bits contained within the data bit positions of each received octet. The block RA1 receives the second bitstream at the intermediate data rate from the block RA2 and outputs a third bitstream containing the user data therein at a user data rate to the DTE.
2. Asynchronous data rate adaption
FIG. 4 illustrates the data rate adaption within a TE (e.g., the TE 21) which receives asynchronously transmitted data from a DTE (e.g., the DTE 31). As depicted, the data rate adaption is achieved using three functional blocks RA0, RA1 and RA2. The block RA0 performs asynchronous to synchronous conversion according to the CCITT series V.14 recommendations. This conversion protocol is summarized in table 4.
TABLE 4 ______________________________________ Data Rate No. of RA0/RA1 RA1 rate tolerance No. of stop rate rate (bit/s) (%) data units elements (bit/s) (kbit/s) ______________________________________ 50 .+-.2.5 5 1.5 600 8 75 .+-.2.5 5.7 or 8 1:1,5:2 600 8 110 .+-.2.5 7 or 8 1 or 2 600 8 150 .+-.2.5 7 or 8 1 or 2 600 8 200 .+-.2.5 7 or 8 1 or 2 600 8 300 .+-.2.5 7 or 8 1 or 2 600 8 600 +1 -2.5 7 or 8 1 or 2 600 8 1,200 +1 -2.5 7 or 8 1 or 2 600 8 2,400 +1 -2.5 7 or 8 1 or 2 1,200 8 3,600 +1 -2.5 7 or 8 1 or 2 2,400 8 4,800 +1 -2.5 7 or 8 1 or 2 4,800 8 7,200 +1 -2.5 7 or 8 1 or 2 9,600 16 9,600 +1 -2.5 7 or 8 1 or 2 9,600 16 12,000 +1 -2.5 7 or 8 1 or 2 19,200 32 14,400 +1 -2.5 7 or 8 1 or 2 19,200 32 19,200 +1 -2.5 7 or 8 1 or 2 19,200 32 ______________________________________ As depicted in table 4, the block RA0 produces a synchronous bitstream at a data rate of 2.sup.n .multidot.600 bits/sec, where n=0, 1, 2, 4, 8, 16 or 32 depending on the user data rate. The blocks RA1 and RA2 are the same as described above for synchronous data transmission. Thus, the block RA1 adapts the synchronous bitstream outputted from the block RA0 to an intermediate data rate (2.sup.k .multidot.8 kbit/sec) and the block RA2 adapts the intermediate data rate bitstream outputted from the block RA1 for transmission at the B-channel data rate (64 kbit/sec). Again, the data is transmitted to a receiving TE (via the NT 11) which has circuitry for reversing each of the three aforementioned data rate adaptions. For example, each of the blocks RA0, RA1 and RA2 additionally performs the inverse of the respective data rate adaptions described above on data received from the NT 11.
The aforementioned data rate adaption protocol is suited for the ISDN network shown in FIG. 1. However, the network of FIG. 1 is disadvantageous as only two DTEs may obtain ISDN service simultaneously.
FIG. 5 illustrates another communications network in which more than two DTEs may obtain ISDN service simultaneously on an ISDN basic rate interface. Such a network is disclosed in the above listed U.S. patent application Ser. No. 07/882,784.
A public network circuit 113 (e.g., a central office switch or PABX) is connected via a trunk line (digital subscriber line) 110 to a fractional network termination unit (F-NT) 111. A F-NT is a NT which is also capable of providing full duplex ISDN services to more than two specially adapted TEs, called fractional terminal equipments (F-TEs), simultaneously. This is achieved using a time division multiplexing scheme in which each B-channel is divided into a number of subchannels which subchannels are subsequently allocated to the F-TEs as needed. For example, each B-channel may be divided into N subchannels, where N is an integer.
The two B-channels, referred to as the B1 and B2 channels are combined into a bitstream, having a frame structure as depicted in FIG. 5A, which is transmitted on the S-interface bus. As shown, a standard S/T interface frame structure includes four alternate octets of B1 and B2-channel bits and control bits. To provide N subchannels, each of the standard whole frames is divided into two parts, each referred to as a subframe. Each subframe includes one octet of B1 bits and one octet of B2 bits. The subframes, in turn, are organized into sequential groups of N subframes called multiframes. Illustratively, each multiframe provides a reference for allocating the octets of the subframes to subchannels.
FIG. 5B is a diagram representative of a multiframe structure comprising N subframes where N is a non-negative integer. Each subframe comprises three blocks denoted as B1i, B2i and other wherein i is an integer index between 1 and N. Block B1i and block B2i each represents an octet of B1-channel bits and an octet of B2-channel bits, respectively, and the other bits are simply represented by the block "Other". The bit sequence in each subframe (not shown in FIG. 5B) conforms to the definition in the foregoing description of FIGS. 5A.
As illustrated in FIG. 5B, each of the multiframe structures comprises N octets of B1-channel bits, each octet denoted as B11, B12, . . . , B1N, respectively, and N octets of B2-channel bits, each octet denoted as B21, B22, . . . , B2N, respectively. In view of the aforementioned multiframe structures, the B1-channel may be divided into N lower rate subchannels, denoted as B11, B12, . . . , B1N, each of which comprises one octet per multiframe. The B2-channel may also be divided into N sub B2-channels denoted as B21, B22, . . . , B2N, each of which comprises one octet per multiframe. Since the bandwidth of each B-channel on the S interface bus is 64 kHz, each sub B-channel, B1i or B2i, occupies the bandwidth of 64/N kbps.
A plurality of F-TEs 121, 122, 123 and TEs 124, 125 are connected via the S interface bus 112 to the F-NT 111. The F-TEs 121, 122 and 123 are capable of transmitting and receiving data via a subchannel at a 64/N kbit/sec data rate where N is an integer equal to the number of subchannels per B-channel. The TEs 124, 125 can only transmit data at the B-channel data rate of 64 kbits/sec. Three DTEs 181, 182, 183 are connected to the F-TEs 121, 122 and 123, respectively according to the V-series recommendations.
The aforementioned V.110 data rate adaption protocol cannot properly adapt the data rate of the F-TEs 121, 122 and 123. This is because the V.110 protocol adapts the user data rate of the DTEs to the B-channel data rate of 64 kbits/sec. This B-channel data rate is too fast for use by the F-TEs in communicating over subchannels at a slower 64/N kbits/sec data rate (so that more than two DTEs may obtain simultaneous ISDN services on the network).
It is therefore an object of the present invention to provide for adapting the data rate of DTEs which are connected, according to V-series recommendations, via a F-TE to an ISDN basic rate interface which provides ISDN services to more than two DTEs simultaneously. Additionally, it is an object of the present invention to provide a rate adapter which perform this function and which is transparent to conventional DTEs, F-TEs and NTs. It is a further object of the present invention to provide for V-series data rate adaption using a minimum effort.